Inkjet printers utilize a printhead which contains various electrical and mechanical components for causing ink to be injected onto a print medium to form an image. The printhead includes a semiconductor chip containing ejection devices and a nozzle plate for ejecting ink from the printhead. The chips also contain integrated circuits that are coupled to the ejection devices on the chips. Proper operation of the ejection devices and circuits is impacted by the construction of the chips. Generally, the choice of a starting substrate material plays a key role in determining the final cost and operational properties of an integrated circuit.
Many of the complimentary metal oxide semiconductor (CMOS) integrated circuits fabricated today for ink jet ejector chips use a relatively high-resistance epitaxial layer 4 overlaying a low-resistivity sub-wafer layer 2 (see FIG. 1). A barrier layer 6 and a metallization layer 8 typically overlay the epitaxial layer 4. This fabrication technique results in reduced parasitic resistances between NMOS and PMOS devices, thereby substantially reducing the likelihood of device latch-up. However, fabricating integrated circuits using a relatively high-resistance epitaxial layer 4 overlaying a low-resistivity sub-wafer layer 2 requires additional material and fabrication steps, resulting in a more costly integrated circuit.
An improved inkjet ejector chip having desirable electrical properties and operating characteristics is needed to reduce the manufacturing costs of ink jet printheads.
The foregoing and other needs are met by an inkjet printer including a printhead for printing an image onto a print medium. The printhead includes an ink ejector chip which operates to heat and energize ink contained in the printhead. The chip includes at least one active device, such as a transistor, logic device, etc. operating to control the electrical operation of the chip.
According to one aspect of the invention, an inkjet printer includes a printhead for printing an image onto a print medium. An improved ink ejector chip includes a plurality of ejection devices for causing ink to be expelled from nozzles on the printhead toward a print medium. Circuitry on the chip controls the activation of one or more of the ejection devices. The chip includes at least one active device having power and ground connections. The active device includes a substrate and is devoid of an overlaying epitaxial layer. At least one dielectric layer is disposed on the substrate, and at least one metallic layer is disposed adjacent to the at least one dielectric layer and the substrate. The chip includes a guard ring disposed on the substrate, substantially surrounding the active device. The guard ring tends to prevent latch-up of the active device during operation of the chip. The chip also includes a power lead electrically connected to the active device for providing power to the device and a ground lead electrically connected to the active device.